Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Public
Document Table of Contents

2.4.1.1. Memory Block Optimization

Memory optimization involves moving user-defined read/write enable signals to associated read-and-write clock enable signals for all memory types.

Memory blocks can represent a large fraction of total design dynamic power. Minimizing the number of memory blocks accessed during each clock cycle can significantly reduce memory power.

Figure 15. Memory Block Transformation

In the default implementation of a simple dual-port memory block, write-clock enable signals and read-clock enable signals connect to VCC, making both read and write memory ports active during each clock cycle.

Memory transformation moves the read-enable and write-enable signals to the respective read-clock enable and write-clock enable signals. This technique reduces the design’s memory power consumption, because memory ports are shut down when they are not accessed.

For Stratix® IV and Stratix® V devices, the memory transformation takes place at the Fitter level by selecting the Normal compilation settings for the power optimization option.

In Cyclone® IV GX and Stratix® IV devices, the read-during-write behavior impacts the power of single-port and bidirectional dual-port RAMs. As a best practice, you can allow optimization by setting the read-during-write parameter to “Don’t care” at the HDL level, and set the read-enable signal to the inversion of the existing write-enable signal (if one exists). This allows the core of the RAM to shut down, which prevents switching, saving a significant amount of power.

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