Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization
ID
683506
Date
9/24/2018
Public
1.1. Comparison of the EPE and the Intel® Quartus® Prime Power Analyzer
1.2. Power Estimations and Design Requirements
1.3. Power Analyzer Walkthrough
1.4. Inputs for the Power Analyzer
1.5. Power Analysis in Modular Design Flows
1.6. Power Analyzer Compilation Report
1.7. Scripting Support
1.8. Power Analysis Revision History
1.4.2.1. Waveforms from Supported Simulators
1.4.2.2. .vcd Files from Third-Party Simulation Tools
1.4.2.3. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation
1.4.2.4. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities
1.4.2.5. Signal Activities from User Defaults Only
1.5.1. Complete Design Simulation
1.5.2. Modular Design Simulation
1.5.3. Multiple Simulations on the Same Entity
1.5.4. Overlapping Simulations
1.5.5. Partial Simulations
1.5.6. Node Name Matching Considerations
1.5.7. Glitch Filtering
1.5.8. Node and Entity Assignments
1.5.9. Default Toggle Rate Assignment
1.5.10. Vectorless Estimation
2.5.1. Clock Power Management
2.5.2. Pipelining and Retiming
2.5.3. Architectural Optimization
2.5.4. I/O Power Guidelines
2.5.5. Memory Optimization (M20K/MLAB)
2.5.6. DDR Memory Controller Settings
Power-Down Mode
Self-Refresh
2.5.7. DSP Implementation
2.5.8. Reducing High-Speed Tile (HST) Usage
2.5.9. Unused Transceiver Channels
2.5.10. Periphery Power reduction XCVR Settings
2.5.6. DDR Memory Controller Settings
The Intel® Arria® 10 EMIF IP DDR3 controller provides low power mode options. These options put DDR in Power saving mode when the controller is idle, providing power savings on External Memory DDR. These options are Enable Auto Power-Down and Auto Power-Down Cycles.
Power-Down Mode
Enable Auto Power-Down directs the controller to place the memory device in power-down mode after a specific number of idle controller clock cycles. You can configure the idle wait time. All ranks must be idle to enter auto power-down.
Auto Power-Down Cycles Number of cycles the controller must be IDLE before entering power down state. You determine the number based on the traffic pattern. If the number is too small, the control enters power down too frequently, affecting efficiency. The Intel® Arria® 10 device family supports from 1 to 65534 cycles.
Figure 28. Intel® Arria® 10 EMIF Controller Parameters
Self-Refresh
Directs the Controller to self-refresh when not sending traffic for very long period. Self-refresh takes more time compared to power down, but the power saving is higher than power down.
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