2.2. Power Dissipation
The following figure shows the power dissipation of Stratix® and Cyclone® devices in different designs. The analysis considers a fixed clock rate of 100 MHz and exhibits varied logic resource utilization across available resources.
In Stratix® and Cyclone® device families, a series of column and row interconnect wires of varying lengths provide signal interconnections between logic array blocks (LABs), memory block structures, and digital signal processing (DSP) blocks or multiplier blocks. These interconnects dissipate the largest component of device power.
FPGA combinational logic is another source of power consumption. For more information about ALMs and LEs in Cyclone® or Stratix® devices, refer to the respective device handbook.
Memory and clock resources are other major consumers of power in FPGAs. Stratix® devices feature the TriMatrix memory architecture. TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit M-RAM blocks, which are configurable to support many features. Stratix® IV TriMatrix on-chip memory is an enhancement based upon the Stratix® II FPGA TriMatrix memory and includes three sizes of memory blocks: MLAB blocks, M9K blocks, and M144K blocks. Stratix® IV and Stratix® V devices feature Programmable Power Technology, an advanced architecture that enables a smooth trade-off between speed and power. The core of each Stratix® IV and Stratix® V device is divided into tiles, each of which may be put into a high-speed or low-power mode. The primary benefit of Programmable Power Technology is to reduce static power, with a secondary benefit being a small reduction in dynamic power. Cyclone® IV GX devices have 9-Kbit M9K memory blocks.
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