Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Public
Document Table of Contents

2.5.1.1.1. Memory Power Reduction Example

Power usage measurements for a 4K × 36 simple dual-port memory implemented using multiple M4K blocks in a Stratix® device. For each implementation, the M4K blocks are configured with a different memory depth.
Table 11.  4K × 36 Simple Dual-Port Memory Implemented Using Multiple M4K Blocks
M4K Configuration Number of M4K Blocks ALUTs
4K × 1 (Default setting) 36 0
2K × 2 36 40
1K × 4 36 62
512 × 9 32 143
256 × 18 32 302
128 × 36 32 633

Using the MAXIMUM_DEPTH parameter can save power. For all implementations, a user-provided read enable signal is present to indicate when read data is required. Using this power-saving technique can reduce power consumption by as much as 60%.

Figure 24. Power Savings Using the MAXIMUM_DEPTH Parameter

As the memory depth becomes more shallow, memory dynamic power decreases because unaddressed M4K blocks can be shut off using a decoded combination of address bits and the read enable signal. For a 128-deep memory block, power used by the extra LEs starts to outweigh the power gain achieved by using a more shallow memory block depth. The power consumption of the memory blocks and associated LEs depends on the memory configuration.

Note: The SOPC Builder and Platform Designer (Standard) system do not offer specific power savings control for on-chip memory block. There is no read enable, write enable, or clock enable that you can enable in the on-chip RAM megafunction to shut down the RAM block in the SOPC Builder and Platform Designer (Standard) system.

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