2. Power Optimization
This chapter describes the power-driven compilation feature and flow in detail, as well as low power design techniques that can further reduce power consumption in your design. The techniques primarily target Arria® , Stratix® , and Cyclone® series of devices. These devices utilize a low-k dielectric material that dramatically reduces dynamic power and improves performance. Arria® series, Stratix® IV, and Stratix® V device families include efficient logic structures called adaptive logic modules (ALMs) that obtain maximum performance while minimizing power consumption. Cyclone® device families offer the optimal blend of high performance and low power in a low-cost FPGA.
This chapter focuses on design optimization options and techniques that help reduce core dynamic power and I/O power. In addition to these techniques, there are additional power optimization techniques available for specific devices, including Programmable Power Technology and Device Speed Grade Selection.
Factors Affecting Power Consumption
Design Space Explorer II for Power-Driven Optimization
Power Optimization Advisor
Power Optimization Revision History
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