Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Public
Document Table of Contents

2.5.1.5. Merge Clocks

Evaluate the possibility of merging clocks and PLLs in the design.

Design 2clks & 2PLLs 1 Clk & 1 PLL

Oc_dma_stamp25

6.079W 5.46W
  • 2clks & 2PLLs

    Clk1:350Mhz, Fanout 46788

    Clk2: 365Mhz, Fanout 2450

  • 1Clk & 1PLL

    Merge clks

    clk: 365Mhz, Fanout 51277

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