Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Public
Document Table of Contents

2.5.8. Reducing High-Speed Tile (HST) Usage

High-Speed tiles are available in Stratix® V and Intel® Arria® 10 device families.
  1. In the Advanced Fitter Settings pane, The Programmable Power Technology Optimization logic option controls how the fitter configures tiles to operate in high-speed mode or low-power mode. Select Minimize Power Only.
    Figure 36.  Programmable Power Technology Optimization
  2. Identify entity modules that use HST by plotting entity modules and HST heatmap on the Chip Planner and modify the floorplan to reduce usage.
    Figure 37.  Entity Modules and HST Heatmap on the Chip Planner

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