Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Document Table of Contents

1.5.2. Modular Design Simulation

You can independently simulate of the top-level design, and then import all the resulting .vcd files into the Power Analyzer. For example, you can simulate the 8b10b_dec independent of the entire design and mux, 8b10b_rxerr, and 8b10b_enc. You can then import the .vcd files generated from each simulation by specifying the appropriate instance name. For example, if the files produced by the simulations are 8b10b_dec.vcd, 8b10b_enc.vcd, 8b10b_rxerr.vcd, and mux.vcd, you can use the import specifications in the following table:

Table 2.  Import Specifications
File Name Entity
8b10b_dec.vcd Top|8b10b_dec:decode1
8b10b_dec.vcd Top|8b10b_dec:decode2
8b10b_dec.vcd Top|8b10b_dec:decode3
8b10b_rxerr.vcd Top|8b10b_rxerr:err1
8b10b_enc.vcd Top|8b10b_enc:encode1
mux.vcd Top|mux:mux1

The resulting power analysis applies the simulation vectors in each file to the assigned entity. Simulation provides signal activities for the pins and for the outputs of functional blocks. If the inputs to an entity instance are input pins for the entire design, the simulation file associated with that instance does not provide signal activities for the inputs of that instance. For example, an input to an entity such as mux1 has its signal activity specified at the output of one of the decode entities.

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