Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 9/24/2018
Document Table of Contents
Give Feedback Timing Assignments to Clock Nodes

For clock nodes, the Power Analyzer uses timing requirements to derive the toggle rate when neither simulation data nor user-entered signal-activity data is available. fMAX requirements specify full cycles per second, but each cycle represents a rising transition and a falling transition. For example, a clock fMAX requirement of 100 MHz corresponds to 200 million transitions per second for the clock node.