Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Public
Document Table of Contents

2.4.2. Power-Driven Fitter

The Intel® Quartus® Prime software allows you to control the power-driven compilation setting of the Fitter on a project-wide basis. The Advanced Fitter Settings dialog box page provides the Power optimization during Fitting logic option, that determines how aggressively the Fitter optimizes the design for power.
Table 9.  Power-Driven Fitter Option
Option Description
Off The Fitter does not perform optimizations to minimize power.
Normal compilation (Default)

The Fitter applies low compute effort algorithms to minimize power through placement and routing optimizations. These techniques do not reduce design performance.

Includes DSP optimizations that create power-efficient DSP block configurations for DSP functions.

Extra effort Besides the optimization techniques of the Normal Compilation option, the Fitter applies high compute effort algorithms to minimize power through placement and routing optimizations. These techniques might impact performance.

The Extra effort setting for the Fitter requires extensive effort to optimize the design for power and can increase compilation time.

For Stratix® IV and Stratix® V devices, the Normal compilation setting enables the Programmable Power Technology to configure tiles as high-speed mode or low-power mode. Programmable Power Technology is always turned ON even when the OFF setting is selected for the Power optimization option. Tiles are the combination of LAB and MLAB pairs (including the adjacent routing associated with LAB and MLAB), which can be configured to operate in high-speed or low-power mode. This level of power optimization does not have any affect on the fitting, timing results, or compile time.

The Extra effort setting the Fitter works to minimize power even after the design meets timing requirements by moving the logic closer during placement to localize high-toggling nets and choosing routes with low capacitance.

The Extra effort setting uses a Value Change Dump (.vcd) file that guides the Fitter to fully optimize the design for power, based on the signal activity of the design. The best power optimization during fitting results from using the most accurate signal activity information. If there is no .vcd file, the Intel® Quartus® Prime software estimates the signal activities from the settings in the Power Analyzer Settings page in the Settings dialog box, such as assignments, clock assignments, and vectorless estimation values. The benchmark data shows that the power-driven Fitter technique can reduce power consumption by as much as 19% in Stratix® devices. On average, you can reduce core dynamic power by 16% with the Extra effort synthesis and Extra effort fitting settings, as compared to the Off settings in both synthesis and Fitter options for power-driven compilation.

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