Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Public
Document Table of Contents

2.4.1. Power-Driven Synthesis

Synthesis netlist optimization occurs during the synthesis stage of the compilation flow. You can apply these settings on a project or entity level.

The Power Optimization During Synthesis logic option determines how aggressively Analysis & Synthesis optimizes the design for power. To access this option at a project level, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis).

Table 7.  Power Optimization During Synthesis Options
Settings Description Optimization Techniques Included
Off The Compiler does not perform netlist, placement, or routing optimizations to minimize power. -
Normal compilation (Default) The Compiler applies low compute effort algorithms to minimize power through netlist optimizations that do not reduce design performance.
  • Memory block optimization
  • Power-aware logic mapping
Extra effort Besides the techniques in the Normal compilation setting, the Compiler applies high-compute-effort algorithms to minimize power through netlist optimizations. Selecting this option might impact performance.
  • Memory block optimization
  • Power-aware logic mapping
  • Power-aware memory balance

You can also control memory optimization options from the Intel® Quartus® Prime Settings dialog box. The Default Parameters page allows you to edit the Low_Power_Mode parameter. The settings for this parameter are equivalent to the values of the Power Optimization During Synthesis logic options. The Low_Power_Mode parameter always takes precedence over the Optimize Power for Synthesis option for power optimization on memory.

Table 8.  Low Power Mode Parameter Options
Parameter Value Equivalent Setting in Power Optimization During Synthesis Logic Option
None Off
Auto Normal compilation
All Extra effort

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