18.104.22.168. Clock Enables
Use clock enables instead of gated clocks:
assign clk_gate = clk1 & gateA & gateB; always @ (posedge clk_gate) begin sr[N-1:1] <= sr[N-2:0]; sr<=din1; end
assign enable = gateA & gateB; always @(posedge clk2) begin if (enable) begin sr[N-1:1] <= sr[N-2:0]; sr<=din2; end end
Reduce LAB-wide clock power consumption without disabling the entire clock tree, use the LAB-wide clock enable to gate the LAB-wide clock.
always @(posedge clk) begin if (ena) temp <= dataa; else temp <= temp; end end
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