Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Public
Document Table of Contents

1.3.2.1.4. Generating a .vcd in a EDA Simulation Tool

To create a .vcd for the design, follow these steps:

  1. On the Assignments > Settings.
  2. In the Category list, under EDA Tool Settings, click Simulation.
  3. In the Tool name list, select the EDA simulator.
  4. In the Format for output netlist list, select Verilog HDL, or SystemVerilog HDL, or VHDL.
  5. Turn on Generate Value Change Dump (VCD) file script.

    This option turns on the Map illegal HDL characters and Enable glitch filtering options.

    The Map illegal HDL characters option ensures that all signals have legal names and makes signal toggle rates available to the Power Analyzer.

    The Enable glitch filtering option directs the EDA Netlist Writer to perform glitch filtering when generating VHDL Output Files, Verilog Output Files, and the corresponding Standard Delay Format Output Files for use with other EDA simulation tools. This option is available regardless of whether or not you want to generate .vcd scripts.
    Note: For ModelSim® simulations , the +nospecify option in the vsim command disables the Specify path delays and timing checks option. By enabling glitch filtering on the Simulation page, the simulation models include specified path delays. Thus, ModelSim® might fail to simulate a design. As a best practice, remove the +nospecify option from the ModelSim® vsim command to ensure accurate simulation for power estimation.
  6. Click Script Settings. Select the signals that you want to write to the .vcd.
    • If you choose All signals, the generated script instructs the third-party simulator to write all connected output signals to the .vcd file.
    • If you choose All signals except combinational lcell outputs, the generated script instructs the third-party simulator to write all connected output signals to the .vcd, except logic cell combinational outputs.
    Note: The file can become extremely large if you write all output signals to the file, because the file size depends on the number of output signals being monitored and the number of transitions that occur.
  7. Click OK.
  8. In the Design instance name box, type a name for the testbench.
  9. Compile the design with the Intel® Quartus® Prime software, and generate the necessary EDA netlist and script that instructs the third-party simulator to generate a .vcd.
  10. In the third-party EDA simulation tool, call the generated script in the simulation tool before running the simulation.
  11. Perform the simulation.
The simulation tool generates the .vcd file in the project directory.

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