Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Public
Document Table of Contents

2.6.1.1. Find Timing Information

  • To find False or Multi-Cycle Paths, click Report Ignored Constraints in the Timing Analyzer Tasks pane.
    Figure 39. Report Ignored Constraints
  • To see a list of the 10 paths with highest delay in the design, in the Reports pane find Fitter Summary Report > Estimate Delay Added for Hold Timing > Details.

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