Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

ID 683506
Date 12/07/2020
Document Table of Contents Generating Signal Activity Data for Power Analysis

Follow these steps to generate and use simulation signal activity data for power analysis:

  1. To run full compilation on your design, click Processing > Start Compilation.
  2. To specify settings for output of simulation files, click Assignments > Settings > EDA Tool Settings > Simulation. Select your simulator in Tool name and the Format for output netlist and Output directory.
  3. Turn on Map illegal HDL characters. This setting directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL, and results in more accurate data for power analysis.
    Figure 6. EDA Tool Settings for Simulation
  4. In the Intel® Quartus® Prime software, click Processing > Power Analyzer Tool. The Power Analyzer tab appears.
  5. Under Input file, turn on Use input files to initialize toggle rates and static probabilities during power analysis, and then click Add Power Input Files. The Power Analyzer Settings page appears.
    Figure 7. Specifying Power Analysis Input Files
  6. To specify a .vcd for power analysis, click Add and specify the File name, Entity, and Simulation period for the .vcd.
  7. To enable glitch filtering during power analysis with the .vcd you generate, turn on Perform glitch filtering on VCD files.
  8. To run the power analysis, click Start on the Power Analyzer tab. View the toggle rates in the power analysis results.

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