Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Document Table of Contents

5.1.1. Generating the Design Example

  1. Download the design example from Design Store.
  2. Using the Quartus® Prime Pro Edition software, restore the file by selecting Open Project and select the .par file. Click OK to load the project
  3. Once the project is successfully loaded, go to IP component tab in Project Navigator pane. Double-click the FIFO Intel® FPGA IP core (fifo1) to open the IP Parameter Editor to examine the IP configuration and regenerate the FIFO IP files.
  4. In the IP Parameter Editor window, ensure that following parameters are set correctly:
    Parameter Value
    How wide should the FIFO be? 20 bits
    How deep should the FIFO be? 32 words
    Read and Write Clock Single clock
    Signals full, empty, usedw[]
    Use Asynchronous Clear Yes
    Use Synchronous Clear Yes
    Memory Block Type MLAB
    FIFO mode Normal
  5. To generate HDL files for this IP core, click Generate HDL. The Generation dialog box appears.
  6. Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
  7. Repeat steps 3 to 6 for FIFO2 Intel® FPGA IP core (fifo2) to examine the IP configuration and regenerate the FIFO2 IP files.
  8. Once the HDL file generation for both FIFO and FIFO2 Intel® FPGA IP is completed, click Tools > Generate Simulator Setup Script for IP to generate a combined simulator setup script that automatically source all the required library files for the FIFO and FIFO2 IP simulation. Use the default directory and click OK to generate the file.