Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1. Release Information for RAM and ROM Intel® FPGA IPs

Intel® FPGA IP versions match the Quartus® Prime Design Suite software versions until v19.1. Starting in Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.

The Intel® FPGA IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:

  • X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 18.  RAM: 1-PORT Intel® FPGA IP Current Release Information

Item

Description

IP Version

20.1.0

Quartus® Prime Version

20.3

Release Date

2020.10.05

Table 19.  RAM: 2-PORT Intel® FPGA IP Current Release Information

Item

Description

IP Version

20.2.1

Quartus® Prime Version

20.3

Release Date

2020.10.05

Table 20.  RAM: 4-PORT Intel® FPGA IP Current Release Information

Item

Description

IP Version

20.1.0

Quartus® Prime Version

20.3

Release Date

2020.10.05

Table 21.  ROM: 1-PORT Intel® FPGA IP Current Release Information

Item

Description

IP Version

20.1.0

Quartus® Prime Version

20.3

Release Date

2020.10.05

Table 22.  ROM: 2-PORT Intel® FPGA IP Current Release Information

Item

Description

IP Version

20.1.0

Quartus® Prime Version

20.3

Release Date

2020.10.05