Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Document Table of Contents

4.3.11. DCFIFO Timing Constraint Setting

The FIFO parameter editor provides the timing constraint setting for the DCFIFO function.

Table 48.  DCFIFO Timing Constraint Setting Parameter in Quartus® Prime Software
Parameter Description
Generate SDC File and disable embedded timing constraint 37 Allows you to bypass embedded timing constraints that uses set_false_path in the synchronization registers. A user configurable SDC file is generated automatically when DCFIFO is instantiated from the IP Catalog. New timing constraints consist of set_net_delay, set_max_skew, set_min_delay and set_max_delay are used to constraint the design properly.
Note: Intel recommends that you select this option for high frequency DCFIFO design to achieve timing closure. For more information, refer to User Configurable Timing Constraint.
37 You can disable the embedded timing constraint with QSF setting in prior Quartus® Prime versions and other devices. Refer to KDB link on the QSF assignment setting.