Visible to Intel only — GUID: eis1414471362957
Ixiasoft
Visible to Intel only — GUID: eis1414471362957
Ixiasoft
4.3.4. FIFO Functional Timing Requirements
If the protection circuitry is not enabled, you must meet the following functional timing requirements:
DCFIFO | SCFIFO |
---|---|
Deassert the wrreq signal in the same clock cycle when the wrfull signal is asserted. | Deassert the wrreq signal in the same clock cycle when the full signal is asserted. |
Deassert the rdreq signal in the same clock cycle when the rdempty signal is asserted. You must observe these requirements regardless of expected behavior based on wrclk and rdclk frequencies. | Deassert the rdreq signal in the same clock cycle when the empty signal is asserted. |


The required functional timing for the DCFIFO as described previously is also applied to the SCFIFO. The difference between the two modes is that for the SCFIFO, the wrreq signal must meet the functional timing requirement based on the full signal and the rdreq signal must meet the functional timing requirement based on the empty signal.
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