Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.2.2.1. eSRAM Specifications

The following table summarizes the specifications of the eSRAM Intel® FPGA IP.
Table 31.  eSRAM Specifications
Feature Detail Value Description
Clock Frequency 6

-1

-2

-3

200 MHz - 750 MHz

200 MHz - 640 MHz

200 MHz - 500 MHz 7
Bank Capacity

without ECC

with ECC

144 Kb

128 Kb

Each bank is (2048) 2K x 72 bits

Banks per Channel

42

Channel Capacity

without ECC

with ECC

5.90625 Mb

5.25 Mb

Channels per eSRAM

8

eSRAM Capacity

without ECC

with ECC

47.25 Mb

42 Mb

Interface Data Width

without ECC

with ECC

x72

Maximum width
Read Latency 8

Normal

Low Power

10 +2 9

11 + 2 9

These latencies are fixed, whether ECC is enabled or not.

Write Latency 0 +1 10 There is a zero cycle latency for write commands issued to the eSRAM.
Power (per eSRAM system)

Industrial

Extended

1.15 W - 1.5 W

2.28 W - 3.31 W

Low Power mode to Normal mode.

6 The input clock source for eSRAM must not exceed 20 ps peak-to-peak, or 1.42 ps RMS at 1e-12 BER, 1.22 ps at 1e-16 BER.
7 In Speed Grade 3 devices, the following clock frequency range is not supported:
  • 466.51 MHz - 499.99 MHz
  • 233.26 MHz - 249.99 MHz
8 Read latency is measured from a read command being presented to the interface to valid read data being returned.
9 +2 on read latency is added due to registers interfacing with eSRAM required to meet routing and timing requirement.
10 +1 on read latency is added due to registers interfacing with eSRAM required to meet routing and timing requirement.