Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Document Table of Contents

2.11. Stratix® 10 Embedded Memory Clocking Modes

Each Stratix® 10 embedded memory operation mode has supporting clocking modes.
Table 11.  Memory Blocks Clocking Modes Supported for Each Memory Mode
Clocking Mode Memory Mode
Single-Port Simple Dual-Port True Dual-Port Simple Quad-Port Single-Port ROM Dual-Port ROM
Single clock mode Yes Yes Yes Yes Yes Yes
Read/write clock mode N/A Yes N/A 1 N/A N/A N/A
Input/output clock mode Yes Yes Yes N/A 2 Yes Yes
Note: The clock enable signals are supported for write address, byte enable, and data input registers on MLAB blocks.
1 The read/write clock mode is done through emulated true dual-port. For more information about the emulated true dual-port, refer to the True Dual Port Dual Clock Emulator section.
2 Both input and output modes share the same clock.