Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Document Table of Contents

4.2.3. eSRAM Intel® FPGA IP Parameters

The parameters allow you to select the channels that you want to implement.
Table 33.  eSRAM Intel® FPGA IP Parameter Editor: General Tab
Parameter Legal Values Description
  • Enable Channel 0
  • Enable Channel 1
  • Enable Channel 2
  • Enable Channel 3
  • Enable Channel 4
  • Enable Channel 5
  • Enable Channel 6
  • Enable Channel 7
On/Off Specifies the channel to be enabled for eSRAM. There are 8 channels per eSRAM.
  • Enable Channel 0—This option enables Channel 0 for eSRAM.
  • Enable Channel 1—This option enables Channel 1 for eSRAM.
  • Enable Channel 2—This option enables Channel 2 for eSRAM.
  • Enable Channel 3—This option enables Channel 3 for eSRAM.
  • Enable Channel 4—This option enables Channel 4 for eSRAM.
  • Enable Channel 5—This option enables Channel 5 for eSRAM.
  • Enable Channel 6—This option enables Channel 6 for eSRAM.
  • Enable Channel 7—This option enables Channel 7 for eSRAM.
PLL Reference Clock Frequency Specifies the PLL reference clock frequency to the eSRAM PLL. The valid ranges is 10 - 325 MHz for any device's speed grade.
PLL Desired Clock Frequency Specifies the PLL desired output clock frequency which is the frequency to the eSRAM. The valid ranges is 200 - 750 MHz depending on the speed grade of your device.
Table 34.  eSRAM Intel® FPGA IP Parameter Editor: Channel Tab
Parameter Legal Values Description
Channel Width and Depth
How wide should the data bus be? Specifies the width of the data bus.
  • Normal mode: 1 to 72 bits
  • ECC enable only: 1 to 64 bits
  • Both ECC and ECC Encoder and Decoder Bypass enabled: 72 bits only
How many words of memory?

Specifies how many memory banks to use out of the possible 42 banks available per eSRAM channel. Banks are specified in increments of 2048 words, where each 2048 words equals one bank. The number of banks specified determines the address width available to the user. Banks that are not used are powered off and cannot be activated after parameterization.

Note: If you attempt to address a bank that has not been enabled, any resulting data will be random and without value.
Channel Features
Enable ECC Encoder and Decoder On/Off Enables the ECC encoder and decoder, which assists in maintaining the integrity of data written to and read from the eSRAM.
Note: When you enable the ECC encoder and decoder, the maximum data bus width decreases from 72 bits to 64 bits. The 8 bit difference is used in the parity calculations required by the ECC encoder and decoder.
Enable Dynamic ECC Encoder and Decoder Bypass On/Off Enables users to dynamically bypass the ECC encoder and/or decoder, by asserting eccencbypass or eccdecbypass. This feature is useful for debugging purposes.
Enable Write Forwarding On/Off Enables write forwarding, which ensures data coherency when writing to and reading from the same address in the eSRAM. Write forwarding takes the data present on the write port and forwards it to the read port as read data.

Write-forwarded read data requires the same duration of time as a regular read. Read logic does not use data stored in the targeted address, but the data is still written to the address.

Enable Low Power Mode On/Off Enables Low Power mode, which reduces power consumption by placing targeted eSRAM memory banks into a state of light sleep. When a bank is targeted for access, it is awakened one cycle prior to the access. The bank returns to a state of light sleep after the access is completed.

Low Power mode does not alter the content of a memory bank. One drawback of Low Power mode is that it increases read latency from 10+2 to 11+2.