Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Document Table of Contents

4.1.8. Changing Parameter Settings Manually

When the IP has been generated using the IP Parameter Editor, you can use this flow to change of the parameter settings within the specified memory mode. However, to change the memory mode, use the IP Parameter Editor to configure and regenerate the IP.

Follow these steps to change the parameter settings manually:

  1. Locate the Verilog design file: <project directory>/<project name_software version>/synth/<projectName_coreName_QuartusVersion_random>.v.
  2. Change the parameter settings in the design file. Ensure that you use only legal parameter values as specified in Parameters and Signals topic. Failing to do so results in compilation errors.
  3. Compile the design using the Quartus® Prime software.

For example, the following codes enable the ECC feature and specify the initialization file.

altera_syncram_component.enable_ecc = "TRUE",
altera_syncram_component.ecc_pipeline_stage_enabled = "FALSE",
altera_syncram_component.init_file = "mif1.mif",

To disable the ECC feature and specify a different .mif file, make the following changes.

altera_syncram_component.enable_ecc = "FALSE",
altera_syncram_component.ecc_pipeline_stage_enabled = "FALSE",
altera_syncram_component.init_file = "mif2.mif",