Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 6/26/2023
Document Table of Contents

4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing

This section describes the effect of the large skew between gray-code counter bits transfers at the clock domain crossing (CDC) with recommended solution. The gray-code counter is 1-bit transition occurs while other bits remain stable when transferring data from the write domain to the read domain and vice versa. If the destination domain latches on the data within the metastable range (violating setup or hold time), only 1 bit is uncertain and destination domain reads the counter value as either an old counter or a new counter. In this case, the DCFIFO still works, as long as the counter sequence is not corrupted.

The following section shows an example of how large skew between the gray-code counter bits can corrupt the counter sequence. Taking a counter width with 3-bit wide and assuming it is transferred from write clock domain to read clock domain. Assume all the counter bits have 0 delay relative to the destination clock, excluding the bit[0] that has delay of 1 clock period of source clock. That is, the skew of the counter bits is 1 clock period of the source clock when they arrived at the destination registers.

The following shows the correct gray-code counter sequence:


which then transfers the data to the read domain, and on to the destination bus registers.

Because of the skew for bit[0], the destination bus registers receive the following sequence:


Because of the skew, a 2-bit transition occurs. This sequence is acceptable if the timing is met. If the 2-bit transition occurs and both bits violate timing, it may result in the counter bus settled at a future or previous counter value, which corrupts the DCFIFO.

Therefore, the skew must be within a certain skew to ensure that the sequence is not corrupted.

Note: Use the report_max_skew and report_net_delay reports in the Timing Analyzer for timing verification if you use the User Configurable Timing Constraint. For Embedded Timing Constraint, use the skew_report.tcl to analyze the actual skew and required skew in your design.

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