Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Document Table of Contents

4.3.12. Coding Example for Manual Instantiation

This section provides a Verilog HDL coding example to create an instance of the DCFIFO. It is not a complete coding for you to compile, but it provides a guideline and some comments for the required structure of the instantiation. You can use the same structure to instantiate other IP cores but only with the ports and parameters that are applicable to the IP cores you instantiated.

Verilog HDL Coding Example to Instantiate the DCFIFO

//module declaration
module dcfifo8x32 (aclr, data, …… ,wfull);
//Module's port declarations
input aclr;
input [31:0] data;
output wrfull;
//Module’s data type declarations and assignments
wire rdempty_w;
wire wrfull = wrfull_w; wire [31:0] q = q_w;
/*Instantiates dcfifo megafunction. Must declare all the ports available from the megafunction and 
define the connection to the module's ports.
Refer to the ports specification from the user guide for more information about the megafunction's 
//syntax: <megafunction's name> <given an instance name>
dcfifo inst1 (
//syntax: .<dcfifo's megafunction's port>(<module's port/wire>)
.wrclk (wrclk),
.rdclk (rdclk),
.wrusedw ()); //left the output open if it's not used
/*Start with the keyword “defparam”, defines the parameters and value assignments. Refer to 
parameters specifications from the user guide for more information about the megafunction's 
//syntax: <instance name>.<parameter> = <value>
inst1.intended_device_family = "Stratix 10", 
inst1.lpm_numwords = 8,
inst1.wrsync_delaypipe = 4;