Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Document Table of Contents

4.2. eSRAM Intel® FPGA IP

The basic building block of the eSRAM Intel® FPGA IP is a bank, which consists of an array of 2K x 72-bit SRAM blocks.

42 eSRAM banks combine to form a channel.

Figure 30. eSRAM Channel

Eight memory channels combine to form an eSRAM system.

Figure 31. eSRAM System