Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Document Table of Contents

4.4.7. FIFO2 Intel® FPGA IP Interface Signals

This section provides diagrams of the SCFIFO and DCFIFO blocks of the FIFO2 Intel® FPGA IP core to help in visualizing their input and output ports. This section also describes each port in detail to help in understanding their usages, functionality, or any restrictions.
Figure 52. FIFO2 IP Core Input and Output Signals