Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Document Table of Contents

4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features

The Shift Register (RAM-based) Intel® FPGA IP implements a shift register with taps and offers additional features, which include:
  • Selectable RAM block type
  • A wide range of widths for the shiftin and shiftout ports
  • Support for output taps at certain points in the shift register chain
  • Selectable distance between taps