Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Public
Document Table of Contents

2.11.4. Asynchronous/Synchronous Clears in Clocking Modes

In all clocking modes, asynchronous and synchronous clears are available only for output latches and output registers.

For the independent (read/write and input/output) clock modes, the asynchronous and synchronous clears are available on both ports.