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1. Stratix® 10 Embedded Memory Overview
2. Stratix® 10 Embedded Memory Architecture and Features
3. Stratix® 10 Embedded Memory Design Considerations
4. Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Stratix® 10 Embedded Memory User Guide
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks
2.2. Address Clock Enable Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Force-to-Zero
2.6. Coherent Read Memory
2.7. Freeze Logic
2.8. True Dual Port Dual Clock Emulator
2.9. 'X' Propagation Support in Simulation
2.10. Stratix® 10 Supported Embedded Memory IPs
2.11. Stratix® 10 Embedded Memory Clocking Modes
2.12. Stratix® 10 Embedded Memory Configurations
2.13. Initial Value of Read and Write Address Registers
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Including the Reset Release Intel® FPGA IP in Your Design
3.9. Resource and Timing Optimization Feature in MLAB Blocks
3.10. Consider the Memory Depth Setting
3.11. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. RAM and ROM Interface Signals
4.1.8. Changing Parameter Settings Manually
4.3.1. Release Information for FIFO Intel® FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO Intel® FPGA IP Parameters
4.3.17. Reset Scheme
4.4.1. Release Information for FIFO2 Intel® FPGA IP
4.4.2. Configuration Methods
4.4.3. Fmax Target Measuring Methodology
4.4.4. Performance Considerations
4.4.5. FIFO2 Intel® FPGA IP Features
4.4.6. FIFO2 Intel® FPGA IP Parameters
4.4.7. FIFO2 Intel® FPGA IP Interface Signals
4.4.8. Reset and Clock Schemes
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.5.5. Shift Register Ports and Parameters Setting
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4.3.6. FIFO Output Status Flag and Latency
The main concern in most FIFO design is the output latency of the read and write status signals.
Output Mode | Optimization Option 24 | Output Latency (in number of clock cycles) |
---|---|---|
Normal 25 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 2 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq / rdreq to empty : 1 | ||
wrreq / rdreq to usedw[] : 1 | ||
rdreq to q[]: 1 | ||
Show-ahead 25 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 3 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 3 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq to empty: 2 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 2 | ||
rdreq to q[]: 1 |
Output Mode | Optimization Option 26 | Output Latency (in number of clock cycles) |
---|---|---|
Normal 27 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 1 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq / rdreq to empty : 1 | ||
wrreq / rdreq to usedw[] : 1 | ||
rdreq to q[]: 1 | ||
Show-ahead 27 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 1 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 1 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq to empty: 1 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 1 | ||
rdreq to q[]: 1 |
Output Latency (in number of clock cycles) |
---|
wrreq to wrfull: 1 wrclk |
wrreq to rdfull: 2 wrclk cycles + following n rdclk 28 |
wrreq to wrempty: 1 wrclk |
wrreq to rdempty: 2 wrclk 29 + following n rdclk 29 |
wrreq to wrusedw[]: 2 wrclk |
wrreq to rdusedw[]: 2 wrclk + following n + 1 rdclk 29 |
wrreq to q[]: 1 wrclk + following 1 rdclk 29 |
rdreq to rdempty: 1 rdclk |
rdreq to wrempty: 1 rdclk + following n wrclk 29 |
rdreq to rfull: 1 rdclk |
rdreq to wrfull: 1 rdclk + following n wrclk 29 |
rdreq to rdusedw[]: 2 rdclk |
rdreq to wrusedw[]: 1 rdclk + following n + 1 wrclk 29 |
rdreq to q[]: 1 rdclk |
24 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
25 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
26 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
27 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
28 The number of n cycles for rdclk and wrclk is equivalent to the number of synchronization stages and are related to the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters. For more information about how the actual synchronization stage (n) is related to the parameters set for different target device, refer to FIFO Metastability Protection and Related Options .
29 This is applied only to Show-ahead output modes. Show-ahead output mode is equivalent to setting the LPM_SHOWAHEAD parameter to ON.