1. Stratix® 10 Embedded Memory Overview
2. Stratix® 10 Embedded Memory Architecture and Features
3. Stratix® 10 Embedded Memory Design Considerations
4. Stratix® 10 Embedded Memory IP References
5. Stratix 10 Embedded Memory Design Example
6. Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Stratix® 10 Embedded Memory User Guide
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks
2.2. Address Clock Enable Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Force-to-Zero
2.6. Coherent Read Memory
2.7. Freeze Logic
2.8. True Dual Port Dual Clock Emulator
2.9. 'X' Propagation Support in Simulation
2.10. Stratix® 10 Supported Embedded Memory IPs
2.11. Stratix® 10 Embedded Memory Clocking Modes
2.12. Stratix® 10 Embedded Memory Configurations
2.13. Initial Value of Read and Write Address Registers
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Including the Reset Release FPGA IP in Your Design
3.9. Resource and Timing Optimization Feature in MLAB Blocks
3.10. Consider the Memory Depth Setting
3.11. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM IPs
4.1.2. RAM: 1-PORT FPGA IP Parameters
4.1.3. RAM: 2-PORT FPGA IP Parameters
4.1.4. RAM: 4-PORT FPGA IP Parameters
4.1.5. ROM: 1-PORT FPGA IP Parameters
4.1.6. ROM: 2-PORT FPGA IP Parameters
4.1.7. RAM and ROM Interface Signals
4.1.8. Changing Parameter Settings Manually
4.3.1. Release Information for FIFO FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO IP Parameters
4.3.17. Reset Scheme
4.3.11.2.1. SDC Commands
SDC Command | Fitter | Timing Analyzer | Recommended Settings |
---|---|---|---|
set_max_skew 41 | To constraint placement and routing of flops in the multi-bit CDC paths to meet the specified skew requirement among bits. | To analyze whether the specified skew requirement is fully met. Both clock and data paths are taken into consideration. |
Set to less than 1 launch clock. |
set_net_delay | Similar to set_max_skew but without taking clock skews into considerations. To ensure the crossing latency is bounded. |
To analyze whether the specified net delay requirement is fully met. Clock paths are not taken into consideration. |
This is currently set to be less than 1 latch clock. 42 |
set_min_delay/set_max_delay | To relax fitter effort by mimicking the set_false_path command but without overriding other SDCs. 43 |
To relax timing analysis for the setup/hold checks to not fail. 44 |
This is currently set to 100ns/-100ns for max/min. 45 |
41 It can have significant compilation time impact in older Quartus versions without Timing Analyzer 2.
42 For advanced users, you can fine-tune the value based on your design. For instance, if the designs are able to tolerate longer crossing latency (full and empty status can be delayed), this can be relaxed.
43 Without set_false_path (which has the highest precedence and may result in very long insertion delays), Fitter attempts to meet the default setup/hold which is extremely over constraint.
44 Without set_false_path, the CDC paths will be analyzed for default setup/hold, which is extremely over constraint.
45 Expect an approximately 100 ns delay when you observe CDC paths compared to set_false_path.