Intel® Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
Public
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Transceiver Channels

All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a hardened Physical Coding Sublayer (PCS).
  • The PMA provides primary interfacing capabilities to physical channels.
  • The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.

A transceiver channel consists of a PMA and a PCS block. Most transceiver banks have 6 channels. There are some transceiver banks that contain only 3 channels.

A wide variety of bonded and non-bonded data rate configurations is possible using a highly configurable clock distribution network. Up to 80 independent transceiver data rates can be configured.

The following figures are graphical representations of top views of the silicon die, which correspond to reverse views for flip chip packages. Different Intel® Arria® 10 devices may have different floorplans than the ones shown in the figures.

Figure 7. Device Chip Overview for Intel® Arria® 10 GX and GT Devices


Figure 8. Device Chip Overview for Intel® Arria® 10 SX Devices


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