Arria® 10 Device Overview

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ID 683332
Date 6/04/2025
Public
Document Table of Contents
Document Table of Contents x
Arria® 10 Device Overview
Arria® 10 Device Overview x
Key Advantages of Arria® 10 Devices Summary of Arria® 10 Features Arria® 10 Device Variants and Packages I/O Vertical Migration for Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Arria® 10 Device Overview
Arria® 10 Device Variants and Packages x
Arria® 10 GX Arria® 10 GT Arria® 10 SX
Arria® 10 GX x
Available Options Maximum Resources Package Plan
Arria® 10 GT x
Available Options Maximum Resources Package Plan
Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Arria® 10 Device Overview

Transceiver Channels

All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a hardened Physical Coding Sublayer (PCS).
  • The PMA provides primary interfacing capabilities to physical channels.
  • The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.

A transceiver channel consists of a PMA and a PCS block. Most transceiver banks have 6 channels. There are some transceiver banks that contain only 3 channels.

A wide variety of bonded and non-bonded data rate configurations is possible using a highly configurable clock distribution network. Up to 80 independent transceiver data rates can be configured.

The following figures are graphical representations of top views of the silicon die, which correspond to reverse views for flip chip packages. Different Arria® 10 devices may have different floorplans than the ones shown in the figures.

Figure 7. Device Chip Overview for Arria® 10 GX and GT Devices


Figure 8. Device Chip Overview for Arria® 10 SX Devices


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