Arria® 10 Device Overview

ID 683332
Date 2/14/2022
Document Table of Contents

SoC with Hard Processor System

Each SoC device combines an FPGA fabric and a hard processor system (HPS) in a single device. This combination delivers the flexibility of programmable logic with the power and cost savings of hard IP in these ways:

  • Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor
  • Allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard
  • Extends the product life and revenue through in-field hardware and software updates
Figure 9. HPS Block DiagramThis figure shows a block diagram of the HPS with the dual ARM Cortex-A9 MPCore processor.