Arria® 10 Device Overview

Download PDF
ID 683332
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

Key Advantages of 20-nm HPS

The 20-nm HPS strikes a balance between enabling maximum software compatibility with 28-nm SoCs while still improving upon the 28-nm HPS architecture. These improvements address the requirements of the next generation target markets such as wireless and wireline communications, compute and storage equipment, broadcast and military in terms of performance, memory bandwidth, connectivity via backplane and security.

Table 24.  Improvements in 20 nm HPSThis table lists the key improvements of the 20 nm HPS compared to the 28 nm HPS.
Advantages/Improvements Description
Increased performance and overdrive capability

While the nominal processor frequency is 1.2 GHz, the 20 nm HPS offers an “overdrive” feature which enables a higher processor operating frequency. This requires a higher supply voltage value that is unique to the HPS and may require a separate regulator.

Increased processor memory bandwidth and DDR4 support

Up to 64-bit DDR4 memory at 2,400 Mbps support is available for the processor. The hard memory controller for the HPS comprises a multi-port front end that manages connections to a single port memory controller. The multi-port front end allows logic core and the HPS to share ports and thereby the available bandwidth of the memory controller.

Flexible I/O sharing

An advanced I/O pin muxing scheme allows improved sharing of I/O between the HPS and the core logic. The following types of I/O are available for SoC:

  • 17 dedicated I/Os—physically located inside the HPS block and are not accessible to logic within the core. The 17 dedicated I/Os are used for HPS clock, resets, and interfacing with boot devices, QSPI, and SD/MMC.
  • 48 direct shared I/O—located closest to the HPS block and are ideal for high speed HPS peripherals such as EMAC, USB, and others. There is one bank of 48 I/Os that supports direct sharing where the 48 I/Os can be shared 12 I/Os at a time.
  • Standard (shared) I/O—all standard I/Os can be shared by the HPS peripherals and any logic within the core. For designs where more than 48 I/Os are required to fully use all the peripherals in the HPS, these I/Os can be connected through the core logic.
EMAC core

Three EMAC cores are available in the HPS. The EMAC cores enable an application to support two redundant Ethernet connections; for example, backplane, or two EMAC cores for managing IEEE 1588 time stamp information while allowing a third EMAC core for debug and configuration. All three EMACs can potentially share the same time stamps, simplifying the 1588 time stamping implementation. A new serial time stamp interface allows core logic to access and read the time stamp values. The integrated EMAC controllers can be connected to external Ethernet PHY through the provided MDIO or I2C interface.

On-chip memory

The on-chip memory is updated to 256 KB support and can support larger data sets and real time algorithms.

ECC enhancements

Improvements in L2 Cache ECC management allow identification of errors down to the address level. ECC enhancements also enable improved error injection and status reporting via the introduction of new memory mapped access to syndrome and data signals.

HPS to FPGA Interconnect Backbone

Although the HPS and the Logic Core can operate independently, they are tightly coupled via a high-bandwidth system interconnect built from high-performance ARM AMBA AXI bus bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS interconnect. Similarly, HPS bus masters have access to bus slaves in the core fabric via the HPS-to-FPGA bridge. Both bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. Up to three masters within the core fabric can share the HPS SDRAM controller with the processor. Additionally, the processor can be used to configure the core fabric under program control via a dedicated 32-bit configuration port.

FPGA configuration and HPS booting

The FPGA fabric and HPS in the SoCs are powered independently. You can reduce the clock frequencies or gate the clocks to reduce dynamic power.

You can configure the FPGA fabric and boot the HPS independently, in any order, providing you with more design flexibility.

Security

New security features have been introduced for anti-tamper management, secure boot, encryption (AES), and authentication (SHA).

Level Two Title