Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

Document Revision History for Intel® Arria® 10 Device Overview

Document Version Changes
2022.02.14 Added notes to Military operating temperature in the Sample Ordering Code and Available Options for Intel® Arria® 10 GX Devices diagram.
2020.10.20 Corrected the maximum count of LVDS pairs for the Intel® Arria® 10 GX 570, GX 660, SX 570, and SX 660 product lines from 324 pairs to 300 pairs.
2018.12.06
  • Added links to Intel® Arria® 10 device errata documents.
  • Removed automotive temperature option from the Intel® Arria® 10 GX devices.
  • Removed –3 fabric speed grade from the Intel® Arria® 10 GT devices.
  • Updated power options for the Intel® Arria® 10 GX and GT devices.
2018.04.09 Updated the lowest VCC from 0.83 V to 0.82 V in the topic listing a summary of the device features.
Date Version Changes
January 2018 2018.01.17
  • Updated the maximum data rate for HPS ( Intel® Arria® 10 SX devices external memory interface DDR3 controller from 2,166 Mbps to 2,133 Mbps.
  • Updated maximum frequency supported for half rate QDRII and QDRII+ SRAM to 633 MHz in Memory Standards Supported by the Soft Memory Controller table.
  • Updated transceiver backplane capability to 12.5 Gbps.
  • Removed transceiver speed grade 5 in Sample Ordering Core and Available Options for Intel® Arria® 10 GX Devices figure.
  • Removed package code 40, low static power, SmartVID, industrial, and military operating temperature support from Sample Ordering Core and Available Options for Intel® Arria® 10 GT Devices figure.
  • Updated short reach transceiver rate for Intel® Arria® 10 GT devices to 25.8 Gbps.
  • Removed On-Die Instrumentation — EyeQ and Jitter Margin Tool support from PMA Features of the Transceivers in Intel® Arria® 10 Devices table.
September 2017 2017.09.20 Updated the maximum speed of the DDR4 external memory interface from 1,333 MHz/2,666 Mbps to 1,200 MHz/2,400 Mbps.
July 2017 2017.07.13 Corrected the automotive temperature range in the figure showing the available options for the Intel® Arria® 10 GX devices from "-40°C to 100°C" to "-40°C to 125°C".
July 2017 2017.07.06 Added automotive temperature option to Intel® Arria® 10 GX device family.
May 2017 2017.05.08
  • Corrected protocol names with "1588" to "IEEE 1588v2".
  • Updated the vertical migration table to remove vertical migration between Intel® Arria® 10 GX and Intel® Arria® 10 SX device variants.
  • Removed all "Preliminary" marks.
March 2017 2017.03.15
  • Removed the topic about migration from Intel® Arria® 10 to Intel® Stratix® 10 devices.
  • Rebranded as Intel.
October 2016 2016.10.31
  • Removed package F36 from Intel® Arria® 10 GX devices.
  • Updated Intel® Arria® 10 GT sample ordering code and maximum GX transceiver count. Intel® Arria® 10 GT devices are available only in the SF45 package option with a maximum of 72 transceivers.
May 2016 2016.05.02
  • Updated the FPGA Configuration and HPS Booting topic.
  • Remove VCC PowerManager from the Summary of Features, Power Management and Arria 10 Device Variants and packages topics. This feature is no longer supported in Arria 10 devices.
  • Removed LPDDR3 from the Memory Standards Supported by the HPS Hard Memory Controller table in the Memory Standards Supported by Intel® Arria® 10 Devices topic. This standard is only supported by the FPGA.
  • Removed transceiver speed grade 5 from the Device Variants and Packages topic for Arria 10 GX and SX devices.
February 2016 2016.02.11
  • Changed the maximum Arria 10 GT datarate to 25.8 Gbps and the minimum datarate to 1 Gbps globally.
  • Revised the state for Core clock networks in the Summary of Features topic.
  • Changed the transceiver parameters in the "Summary of Features for Arria 10 Devices" table.
  • Changed the transceiver parameters in the "Maximum Resource Counts for Arria 10 GT Devices" table.
  • Changed the package availability for GT devices in the "Package Plan for Arria 10 GT Devices" table.
  • Changed the package configurations for GT devices in the "Migration Capability Across Arria 10 Product Lines" figure.
  • Changed transceiver parameters in the "Low Power Serial Transceivers" section.
  • Changed the transceiver descriptions in the "Device Variants for the Arria 10 Device Family" table.
  • Changed the "Sample Ordering Code and Available Options for Arria 10 GT Devices" figure.
  • Changed the datarates for GT devices in the "PMA Features" section.
  • Changed the datarates for GT devices in the "PCS Features" section.
December 2015 2015.12.14
  • Updated the number of M20K memory blocks for Arria 10 GX 660 from 2133 to 2131 and corrected the total RAM bit from 48,448 Kb to 48,408 Kb.
  • Corrected the number of DSP blocks for Arria 10 GX 660 from 1688 to 1687 in the table listing floating-point arithmetic resources.
November 2015 2015.11.02
  • Updated the maximum resources for Arria 10 GX 220, GX 320, GX 480, GX 660, SX 220, SX 320, SX 480, and SX 660.
  • Updated resource count for Arria 10 GX 320, GX 480, GX 660, SX 320, SX 480, a SX 660 devices in Number of Multipliers in Intel® Arria® 10 Devices table.
  • Updated the available options for Arria 10 GX, GT, and SX.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.15 Corrected label for Intel® Arria® 10 GT product lines in the vertical migration figure.
May 2015 2015.05.15 Corrected the DDR3 half rate and quarter rate maximum frequencies in the table that lists the memory standards supported by the Intel® Arria® 10 hard memory controller.
May 2015 2015.05.04
  • Added support for 13.5G JESD204b in the Summary of Features table.
  • Added a link to Arria 10 GT Channel Usage in the Arria 10 GT Package Plan topic.
  • Added a note to the table, Maximum Resource Counts for Arria 10 GT devices.
  • Updated the power requirements of the transceivers in the Low Power Serial Transceivers topic.
January 2015 2015.01.23
  • Added floating point arithmetic features in the Summary of Features table.
  • Updated the total embedded memory from 38.38 megabits (Mb) to 65.6 Mb.
  • Updated the table that lists the memory standards supported by Intel® Arria® 10 devices.
  • Removed support for DDR3U, LPDDR3 SDRAM, RLDRAM 2, and DDR2.
  • Moved RLDRAM 3 support from hard memory controller to soft memory controller. RLDRAM 3 support uses hard PHY with soft memory controller.
  • Added soft memory controller support for QDR IV.
  • Updated the maximum resource count table to include the number of hard memory controllers available in each device variant.
  • Updated the transceiver PCS data rate from 12.5 Gbps to 12 Gbps.
  • Updated the max clock rate of PS, FPP x8, FPP x16, and Configuration via HPS from 125 MHz to 100 MHz.
  • Added a feature for fractional synthesis PLLs: PLL cascading.
  • Updated the HPS programmable general-purpose I/Os from 54 to 62.
September 2014 2014.09.30
  • Corrected the 3 V I/O and LVDS I/O counts for F35 and F36 packages of Arria 10 GX.
  • Corrected the 3 V I/O, LVDS I/O, and transceiver counts for the NF40 package of the Arria GX 570 and 660.
  • Removed 3 V I/O, LVDS I/O, and transceiver counts for the NF40 package of the Arria GX 900 and 1150. The NF40 package is not available for Arria 10 GX 900 and 1150.
August 2014 2014.08.18
  • Updated Memory (Kb) M20K maximum resources for Arria 10 GX 660 devices from 42,660 to 42,620.
  • Added GPIO columns consisting of LVDS I/O Bank and 3V I/O Bank in the Package Plan table.
  • Added how to use memory interface clock frequency higher than 533 MHz in the I/O vertical migration.
  • Added information to clarify that RLDRAM3 support uses hard PHY with soft memory controller.
  • Added variable precision DSP blocks support for floating-point arithmetic.
June 2014 2014.06.19 Updated number of dedicated I/Os in the HPS block to 17.
February 2014 2014.02.21 Updated transceiver speed grade options for GT devices in Figure 2.
February 2014 2014.02.06 Updated data rate for Arria 10 GT devices from 28.1 Gbps to 28.3 Gbps.
December 2013 2013.12.10
  • Updated the HPS memory standards support from LPDDR2 to LPDDR3.
  • Updated HPS block diagram to include dedicated HPS I/O and FPGA Configuration blocks as well as repositioned SD/SDIO/MMC, DMA, SPI and NAND Flash with ECC blocks .
December 2013 2013.12.02 Initial release.
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