Intel® Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
Public
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PCIe Gen1, Gen2, and Gen3 Hard IP

Intel® Arria® 10 devices contain PCIe hard IP that is designed for performance and ease-of-use:

  • Includes all layers of the PCIe stack—transaction, data link and physical layers.
  • Supports PCIe Gen3, Gen2, and Gen1 Endpoint and Root Port in x1, x2, x4, or x8 lane configuration.
  • Operates independently from the core logic—optional configuration via protocol (CvP) allows the PCIe link to power up and complete link training in less than 100 ms while the Intel® Arria® 10 device completes loading the programming file for the rest of the FPGA.
  • Provides added functionality that makes it easier to support emerging features such as Single Root I/O Virtualization (SR-IOV) and optional protocol extensions.
  • Provides improved end-to-end datapath protection using ECC.
  • Supports FPGA configuration via protocol (CvP) using PCIe at Gen3, Gen2, or Gen1 speed.

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