Using partial reconfiguration, you can reconfigure some parts of the device while keeping the device in operation.
Instead of placing all device functions in the FPGA fabric, you can store some functions that do not run simultaneously in external memory and load them only when required. This capability increases the effective logic density of the device, and lowers cost and power consumption.
In the Intel® solution, you do not have to worry about intricate device architecture to perform a partial reconfiguration. The partial reconfiguration capability is built into the Intel® Quartus® Prime design software, making such time-intensive task simple.
Intel® Arria® 10 devices support partial reconfiguration in the following configuration options:
- Using an internal host:
- All supported configuration modes where the FPGA has access to external memory devices such as serial and parallel flash memory.
- Configuration via Protocol [CvP (PCIe)].
- Using an external host—passive serial (PS), fast passive parallel (FPP) x8, FPP x16, and FPP x32 I/O interfaces.
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