Arria® 10 Device Overview

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ID 683332
Date 6/04/2025
Public
Document Table of Contents
Document Table of Contents x
Arria® 10 Device Overview
Arria® 10 Device Overview x
Key Advantages of Arria® 10 Devices Summary of Arria® 10 Features Arria® 10 Device Variants and Packages I/O Vertical Migration for Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Arria® 10 Device Overview
Arria® 10 Device Variants and Packages x
Arria® 10 GX Arria® 10 GT Arria® 10 SX
Arria® 10 GX x
Available Options Maximum Resources Package Plan
Arria® 10 GT x
Available Options Maximum Resources Package Plan
Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Arria® 10 Device Overview

Enhanced Configuration and Configuration via Protocol

Table 25.  Configuration Schemes and Features of Arria® 10 Devices Arria® 10 devices support 1.8 V programming voltage and several configuration schemes.
Scheme Data Width

Max Clock Rate

(MHz)

Max Data Rate

(Mbps)

13 		Decompression Design Security 14 Partial Reconfiguration 15 Remote System Update
JTAG 1 bit 33 33 — — Yes 16 —
Active Serial (AS) through the EPCQ-L configuration device

1 bit,

4 bits

 100 400 Yes Yes Yes 16 Yes
Passive serial (PS) through CPLD or external microcontroller 1 bit 100 100 Yes Yes Yes 16 Parallel Flash Loader (PFL) Intel® FPGA IP core
Fast passive parallel (FPP) through CPLD or external microcontroller 8 bits 100 3200 Yes Yes Yes 17 PFL Intel® FPGA IP core
16 bits Yes Yes
32 bits Yes Yes
Configuration via HPS 16 bits 100 3200 Yes Yes Yes 17 —
32 bits Yes Yes
Configuration via Protocol [CvP ( PCIe* )]

x1, x2, x4, x8 lanes

 — 8000 Yes Yes Yes 16 —

You can configure Arria® 10 devices through PCIe using Configuration via Protocol (CvP). The Arria® 10 CvP implementation conforms to the PCIe* 100 ms power-up-to-active time requirement.

Related Information
13 Enabling either compression or design security features affects the maximum data rate. Refer to the Arria® 10 Device Datasheet for more information.
14 Encryption and compression cannot be used simultaneously.
15 Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial reconfiguration, contact Altera for support.
16 Partial configuration can be performed only when it is configured as internal host.
17 Supported at a maximum clock rate of 100 MHz.
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