Arria® 10 Device Overview

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ID 683332
Date 6/04/2025
Public
Document Table of Contents
Document Table of Contents x
Arria® 10 Device Overview
Arria® 10 Device Overview x
Key Advantages of Arria® 10 Devices Summary of Arria® 10 Features Arria® 10 Device Variants and Packages I/O Vertical Migration for Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Arria® 10 Device Overview
Arria® 10 Device Variants and Packages x
Arria® 10 GX Arria® 10 GT Arria® 10 SX
Arria® 10 GX x
Available Options Maximum Resources Package Plan
Arria® 10 GT x
Available Options Maximum Resources Package Plan
Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Arria® 10 Device Overview

Embedded Memory Capacity in Arria® 10 Devices

Table 18.  Embedded Memory Capacity and Distribution in Arria® 10 Devices
Variant Product Line M20K MLAB Total RAM Bit (Kb)
Block RAM Bit (Kb) Block RAM Bit (Kb)
Arria® 10 GX GX 160 440 8,800 1,680 1,050 9,850
GX 220 587 11,740 2,703 1,690 13,430
GX 270 750 15,000 3,922 2,452 17,452
GX 320 891 17,820 4,363 2,727 20,547
GX 480 1,431 28,620 6,662 4,164 32,784
GX 570 1,800 36,000 8,153 5,096 41,096
GX 660 2,131 42,620 9,260 5,788 48,408
GX 900 2,423 48,460 15,017 9,386 57,846
GX 1150 2,713 54,260 20,774 12,984 67,244
Arria® 10 GT GT 900 2,423 48,460 15,017 9,386 57,846
GT 1150 2,713 54,260 20,774 12,984 67,244
Arria® 10 SX SX 160 440 8,800 1,680 1,050 9,850
SX 220 587 11,740 2,703 1,690 13,430
SX 270 750 15,000 3,922 2,452 17,452
SX 320 891 17,820 4,363 2,727 20,547
SX 480 1,431 28,620 6,662 4,164 32,784
SX 570 1,800 36,000 8,153 5,096 41,096
SX 660 2,131 42,620 9,260 5,788 48,408
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