Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

PMA Features

Intel® Arria® 10 transceivers provide exceptional signal integrity at data rates up to 25.8 Gbps. Clocking options include ultra-low jitter ATX PLLs (LC tank based), clock multiplier unit (CMU) PLLs, and fractional PLLs.

Each transceiver channel contains a channel PLL that can be used as the CMU PLL or clock data recovery (CDR) PLL. In CDR mode, the channel PLL recovers the receiver clock and data in the transceiver channel. Up to 80 independent data rates can be configured on a single Intel® Arria® 10 device.

Table 23.  PMA Features of the Transceivers in Intel® Arria® 10 Devices

Feature

Capability

Chip-to-Chip Data Rates

1 Gbps to 17.4 Gbps ( Intel® Arria® 10 GX devices)

1 Gbps to 25.8 Gbps ( Intel® Arria® 10 GT devices)

Backplane Support

Drive backplanes at data rates up to 12.5 Gbps

Optical Module Support

SFP+/SFP, XFP, CXP, QSFP/QSFP28, CFP/CFP2/CFP4

Cable Driving Support

SFP+ Direct Attach, PCI Express over cable, eSATA

Transmit Pre-Emphasis

4-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss

Continuous Time Linear Equalizer (CTLE)

Dual mode, high-gain, and high-data rate, linear receive equalization to compensate for system channel loss

Decision Feedback Equalizer (DFE)

7-fixed and 4-floating tap DFE to equalize backplane channel loss in the presence of crosstalk and noisy environments

Variable Gain Amplifier Optimizes the signal amplitude prior to the CDR sampling and operates in fixed and adaptive modes

Altera Digital Adaptive Parametric Tuning (ADAPT)

Fully digital adaptation engine to automatically adjust all link equalization parameters—including CTLE, DFE, and variable gain amplifier blocks—that provide optimal link margin without intervention from user logic

Precision Signal Integrity Calibration Engine (PreSICE)

Hardened calibration controller to quickly calibrate all transceiver control parameters on power-up, which provides the optimal signal integrity and jitter performance

Advanced Transmit (ATX) PLL

Low jitter ATX (LC tank based) PLLs with continuous tuning range to cover a wide range of standard and proprietary protocols

Fractional PLLs

On-chip fractional frequency synthesizers to replace on-board crystal oscillators and reduce system cost

Digitally Assisted Analog CDR

Superior jitter tolerance with fast lock time

Dynamic Partial Reconfiguration

Allows independent control of the Avalon memory-mapped interface of each transceiver channel for the highest transceiver flexibility

Multiple PCS-PMA and PCS-PLD interface widths

8-, 10-, 16-, 20-, 32-, 40-, or 64-bit interface widths for flexibility of deserialization width, encoding, and reduced latency

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