Intel® Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX
Available Options Maximum Resources Package Plan
Embedded Memory Blocks
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs
Fractional Synthesis PLLs I/O PLLs
External Memory Interface
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers
Transceiver Channels PMA Features PCS Features
PCS Features
PCS Protocol Support
SoC with Hard Processor System
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

Power Management

Intel® Arria® 10 devices leverage the advanced 20 nm process technology, a low 0.9 V core power supply, an enhanced core architecture, and several optional power reduction techniques to reduce total power consumption by as much as 40% compared to Arria V devices and as much as 60% compared to Stratix V devices.

The optional power reduction techniques in Intel® Arria® 10 devices include:

  • SmartVID—a code is programmed into each device during manufacturing that allows a smart regulator to operate the device at lower core VCC while maintaining performance
  • Programmable Power Technology—non-critical timing paths are identified by the Intel® Quartus® Prime software and the logic in these paths is biased for low power instead of high performance
  • Low Static Power Options—devices are available with either standard static power or low static power while maintaining performance

Furthermore, Intel® Arria® 10 devices feature Intel’s industry-leading low power transceivers and include a number of hard IP blocks that not only reduce logic resources but also deliver substantial power savings compared to soft implementations. In general, hard IP blocks consume up to 90% less power than the equivalent soft logic implementations.

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