FPGA General Purpose I/O
Intel® Arria® 10 devices offer highly configurable GPIOs. Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory controller.
The following list describes the features of the GPIOs:
- Consist of 3 V I/Os for high-voltage application and LVDS I/Os for differential signaling
- Up to two 3 V I/O banks, available in some devices, that support up to 3 V I/O standards
- LVDS I/O banks that support up to 1.8 V I/O standards
- Support a wide range of single-ended and differential I/O interfaces
- LVDS speeds up to 1.6 Gbps
- Each LVDS pair of pins has differential input and output buffers, allowing you to configure the LVDS direction for each pair.
- Programmable bus hold and weak pull-up
- Programmable differential output voltage (VOD) and programmable pre-emphasis
- Series (RS ) and parallel (RT ) on-chip termination (OCT) for all I/O banks with OCT calibration to limit the termination impedance variation
- On-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity
- Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop (DLL) delay chain with fine and coarse architecture
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