Arria® 10 Device Overview

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ID 683332
Date 6/04/2025
Public
Document Table of Contents
Document Table of Contents x
Arria® 10 Device Overview
Arria® 10 Device Overview x
Key Advantages of Arria® 10 Devices Summary of Arria® 10 Features Arria® 10 Device Variants and Packages I/O Vertical Migration for Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Arria® 10 Device Overview
Arria® 10 Device Variants and Packages x
Arria® 10 GX Arria® 10 GT Arria® 10 SX
Arria® 10 GX x
Available Options Maximum Resources Package Plan
Arria® 10 GT x
Available Options Maximum Resources Package Plan
Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Arria® 10 Device Overview

Key Advantages of Arria® 10 Devices

Table 2.   Key Advantages of the Arria® 10 Device Family

Advantage

Supporting Feature

Enhanced core architecture
  • Built on TSMC's 20 nm process technology
  • 60% higher performance than the previous generation of mid-range FPGAs
  • 15% higher performance than the fastest previous-generation FPGA
High-bandwidth integrated transceivers
  • Short-reach rates up to 25.8 Gigabits per second (Gbps)
  • Backplane capability up to 12.5 Gbps
  • Integrated 10GBASE-KR and 40GBASE-KR4 Forward Error Correction (FEC)
Improved logic integration and hard IP blocks
  • 8-input adaptive logic module (ALM)
  • Up to 65.6 megabits (Mb) of embedded memory
  • Variable-precision digital signal processing (DSP) blocks
  • Fractional synthesis phase-locked loops (PLLs)
  • Hard PCI Express Gen3 IP blocks
  • Hard memory controllers and PHY up to 2,400 Megabits per second (Mbps)
Second generation hard processor system (HPS) with integrated ARM* Cortex*-A9* MPCore* processor
  • Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard IP, and an FPGA in a single Arria® 10 system-on-a-chip (SoC)
  • Supports over 128 Gbps peak bandwidth with integrated data coherency between the processor and the FPGA fabric
Advanced power savings
  • Comprehensive set of advanced power saving features
  • Power-optimized MultiTrack routing and core architecture
  • Up to 40% lower power compared to previous generation of mid-range FPGAs
  • Up to 60% lower power compared to previous generation of high-end FPGAs
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