Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

Low Power Serial Transceivers

Intel® Arria® 10 FPGAs and SoCs include lowest power transceivers that deliver high bandwidth, throughput and low latency.

Intel® Arria® 10 devices deliver the industry's lowest power consumption per transceiver channel:

  • 12.5 Gbps transceivers at as low as 242 mW
  • 10 Gbps transceivers at as low as 168 mW
  • 6 Gbps transceivers at as low as 117 mW

Intel® Arria® 10 transceivers support various data rates according to application:

  • Chip-to-chip and chip-to-module applications—from 1 Gbps up to 25.8 Gbps
  • Long reach and backplane applications—from 1 Gbps up to 12.5 with advanced adaptive equalization
  • Critical power sensitive applications—from 1 Gbps up to 11.3 Gbps using lower power modes

The combination of 20 nm process technology and architectural advances provide the following benefits:

  • Significant reduction in die area and power consumption
  • Increase of up to two times in transceiver I/O density compared to previous generation devices while maintaining optimal signal integrity
  • Up to 72 total transceiver channels—you can configure up to 6 of these channels to run as fast as 25.8 Gbps
  • All channels feature continuous data rate support up to the maximum rated speed
Figure 6.  Intel® Arria® 10 Transceiver Block Architecture



Section Content
Transceiver Channels
PMA Features
PCS Features

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