Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
I/O Vertical Migration for Intel® Arria® 10 Devices
Figure 4. Migration Capability Across Intel® Arria® 10 Product Lines
- The arrows indicate the migration paths. The devices included in each vertical migration path are shaded. Devices with fewer resources in the same path have lighter shades.
- To achieve the full I/O migration across product lines in the same migration path, restrict I/Os and transceivers usage to match the product line with the lowest I/O and transceiver counts.
- An LVDS I/O bank in the source device may be mapped to a 3 V I/O bank in the target device. To use memory interface clock frequency higher than 533 MHz, assign external memory interface pins only to banks that are LVDS I/O in both devices.
- There may be nominal 0.15 mm package height difference between some product lines in the same package type.
- Some migration paths are not shown in the Intel® Quartus® Prime software Pin Migration View.
Note: To verify the pin migration compatibility, use the Pin Migration View window in the Intel® Quartus® Prime software Pin Planner.
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