Arria® 10 Device Overview

ID 683332
Date 2/14/2022
Document Table of Contents

Fractional Synthesis PLLs

You can use the fractional synthesis PLLs to:

  • Reduce the number of oscillators that are required on your board
  • Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source

The fractional synthesis PLLs support the following features:

  • Reference clock frequency synthesis for transceiver CMU and Advanced Transmit (ATX) PLLs
  • Clock network delay compensation
  • Zero-delay buffering
  • Direct transmit clocking for transceivers
  • Independently configurable into two modes:
    • Conventional integer mode equivalent to the general purpose PLL
    • Enhanced fractional mode with third order delta-sigma modulation
  • PLL cascading