Arria® 10 Device Overview

ID 683332
Date 2/14/2022
Document Table of Contents

Summary of Intel® Arria® 10 Features

Table 3.  Summary of Features for Intel® Arria® 10 Devices
Feature Description


  • TSMC's 20-nm SoC process technology
  • Allows operation at a lower VCC level of 0.82 V instead of the 0.9 V standard VCC core voltage


  • 1.0 mm ball-pitch Fineline BGA packaging
  • 0.8 mm ball-pitch Ultra Fineline BGA packaging
  • Multiple devices with identical package footprints for seamless migration between different FPGA densities
  • Devices with compatible package footprints allow migration to next generation high-end Stratix® 10 devices
  • RoHS, leaded1, and lead-free (Pb-free) options

High-performance FPGA fabric

  • Enhanced 8-input ALM with four registers
  • Improved multi-track routing architecture to reduce congestion and improve compilation time
  • Hierarchical core clocking architecture
  • Fine-grained partial reconfiguration

Internal memory blocks

  • M20K—20-Kb memory blocks with hard error correction code (ECC)
  • Memory logic array block (MLAB)—640-bit memory

Embedded Hard IP blocks

Variable-precision DSP

  • Native support for signal processing precision levels from 18 x 19 to 54 x 54
  • Native support for 27 x 27 multiplier mode
  • 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
  • Internal coefficient memory banks
  • Preadder/subtractor for improved efficiency
  • Additional pipeline register to increase performance and reduce power
  • Supports floating point arithmetic:
    • Perform multiplication, addition, subtraction, multiply-add, multiply-subtract, and complex multiplication.
    • Supports multiplication with accumulation capability, cascade summation, and cascade subtraction capability.
    • Dynamic accumulator reset control.
    • Support direct vector dot and complex multiplication chaining multiply floating point DSP blocks.

Memory controller

DDR4, DDR3, and DDR3L

PCI Express*

PCI Express (PCIe*) Gen3 (x1, x2, x4, or x8), Gen2 (x1, x2, x4, or x8) and Gen1 (x1, x2, x4, or x8) hard IP with complete protocol stack, endpoint, and root port

Transceiver I/O

  • 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC)
  • PCS hard IPs that support:
    • 10-Gbps Ethernet (10GbE)
    • PCIe PIPE interface
    • Interlaken
    • Gbps Ethernet (GbE)
    • Common Public Radio Interface (CPRI) with deterministic latency support
    • Gigabit-capable passive optical network (GPON) with fast lock-time support
  • 13.5G JESD204b
  • 8B/10B, 64B/66B, 64B/67B encoders and decoders
  • Custom mode support for proprietary protocols

Core clock networks

  • Up to 800 MHz fabric clocking, depending on the application:
    • 667 MHz external memory interface clocking with 2,400 Mbps DDR4 interface
    • 800 MHz LVDS interface clocking with 1,600 Mbps LVDS interface
  • Global, regional, and peripheral clock networks
  • Clock networks that are not used can be gated to reduce dynamic power

Phase-locked loops (PLLs)

  • High-resolution fractional synthesis PLLs:
    • Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
    • Support integer mode and fractional mode
    • Fractional mode support with third-order delta-sigma modulation
  • Integer PLLs:
    • Adjacent to general purpose I/Os
    • Support external memory and LVDS interfaces

FPGA General-purpose I/Os (GPIOs)

  • 1.6 Gbps LVDS—every pair can be configured as receiver or transmitter
  • On-chip termination (OCT)
  • 1.2 V to 3.0 V single-ended LVTTL/LVCMOS interfacing

External Memory Interface

  • Hard memory controller— DDR4, DDR3, and DDR3L support
    • DDR4—speeds up to 1,200 MHz/2,400 Mbps
    • DDR3—speeds up to 1,067 MHz/2,133 Mbps
  • Soft memory controller—provides support for RLDRAM 3 2, QDR IV2, and QDR II+

Low-power serial transceivers

  • Continuous operating range:
    • Intel® Arria® 10 GX—1 Gbps to 17.4 Gbps
    • Intel® Arria® 10 GT—1 Gbps to 25.8 Gbps
  • Backplane support:
    • Intel® Arria® 10 GX—up to 12.5
    • Intel® Arria® 10 GT—up to 12.5
  • Extended range down to 125 Mbps with oversampling
  • ATX transmit PLLs with user-configurable fractional synthesis capability
  • Electronic Dispersion Compensation (EDC) support for XFP, SFP+, QSFP, and CFP optical module
  • Adaptive linear and decision feedback equalization
  • Transmitter pre-emphasis and de-emphasis
  • Dynamic partial reconfiguration of individual transceiver channels


( Intel® Arria® 10 SX devices only)

Processor and system

  • Dual-core ARM Cortex-A9 MPCore processor—1.2 GHz CPU with 1.5 GHz overdrive capability
  • 256 KB on-chip RAM and 64 KB on-chip ROM
  • System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA) controller, FPGA configuration manager, and clock and reset managers
  • Security features—anti-tamper, secure boot, Advanced Encryption Standard (AES) and authentication (SHA)
  • ARM CoreSight* JTAG debug access port, trace port, and on-chip trace storage

External interfaces

  • Hard memory interface—Hard memory controller (2,400 Mbps DDR4, and 2,133 Mbps DDR3), Quad serial peripheral interface (QSPI) flash controller, NAND flash controller, direct memory access (DMA) controller, Secure Digital/MultiMediaCard (SD/MMC) controller
  • Communication interface— 10/100/1000 Ethernet media access control (MAC), USB On-The-GO (OTG) controllers, I2C controllers, UART 16550, serial peripheral interface (SPI), and up to 62 HPS GPIO interfaces (48 direct-share I/Os)

Interconnects to core

  • High-performance ARM AMBA* AXI bus bridges that support simultaneous read and write
  • HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa
  • Configuration bridge that allows HPS configuration manager to configure the core logic via dedicated 32-bit configuration port
  • FPGA-to-HPS SDRAM controller bridge—provides configuration interfaces for the multiport front end (MPFE) of the HPS SDRAM controller


  • Tamper protection—comprehensive design protection to protect your valuable IP investments
  • Enhanced 256-bit advanced encryption standard (AES) design security with authentication
  • Configuration via protocol (CvP) using PCIe* Gen1, Gen2, or Gen3
  • Dynamic reconfiguration of the transceivers and PLLs
  • Fine-grained partial reconfiguration of the core fabric
  • Active Serial x4 Interface

Power management

  • SmartVID
  • Low static power device options
  • Programmable Power Technology
  • Intel® Quartus® Prime integrated power analysis

Software and tools

  • Intel® Quartus® Prime design suite
  • Transceiver toolkit
  • Platform Designer system integration tool
  • DSP Builder for Intel FPGAs
  • OpenCL™ support
  • Intel® SoC FPGA Embedded Design Suite (EDS)
1 Contact Intel for availability.
2 Intel® Arria® 10 devices support this external memory interface using hard PHY with soft memory controller.