Arria® 10 Device Overview

ID 683332
Date 2/14/2022
Document Table of Contents

Features of the HPS

The HPS has the following features:

  • 1.2-GHz, dual-core ARM Cortex-A9 MPCore processor with up to 1.5-GHz via overdrive
    • ARMv7-A architecture that runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java byte codes in Jazelle style
    • Superscalar, variable length, out-of-order pipeline with dynamic branch prediction
    • Instruction Efficiency 2.5 MIPS/MHz, which provides total performance of 7500 MIPS at 1.5 GHz
  • Each processor core includes:
    • 32 KB of L1 instruction cache, 32 KB of L1 data cache
    • Single- and double-precision floating-point unit and NEON media engine
    • CoreSight debug and trace technology
    • Snoop Control Unit (SCU) and Acceleration Coherency Port (ACP)
  • 512 KB of shared L2 cache
  • 256 KB of scratch RAM
  • Hard memory controller with support for DDR3, DDR4 and optional error correction code (ECC) support
  • Multiport Front End (MPFE) Scheduler interface to the hard memory controller 
  • 8-channel direct memory access (DMA) controller
  • QSPI flash controller with SIO, DIO, QIO SPI Flash support
  • NAND flash controller (ONFI 1.0 or later) with DMA and ECC support, updated to support 8 and 16-bit Flash devices and new command DMA to offload CPU for fast power down recovery
  • Updated SD/SDIO/MMC controller to eMMC 4.5 with DMA with CE-ATA digital command support
  • 3 10/100/1000 Ethernet media access control (MAC) with DMA
  • 2 USB On-the-Go (OTG) controllers with DMA
  • 5 I2C controllers (3 can be used by EMAC for MIO to external PHY)
  • 2 UART 16550 Compatible controllers
  • 4 serial peripheral interfaces (SPI) (2 Master, 2 Slaves)
  • 62 programmable general-purpose I/Os, which includes 48 direct share I/Os that allows the HPS peripherals to connect directly to the FPGA I/Os
  • 7 general-purpose timers
  • 4 watchdog timers
  • Anti-tamper, Secure Boot, Encryption (AES) and Authentication (SHA)