AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Document Table of Contents

1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

Updated for:
Intel® Quartus® Prime Design Suite 21.3

Today’s design application and performance requirements are more challenging than ever due to increased complexity. With the evolution of system-on-a-chip, the size of typical designs are ever increasing. Complexities such as external memory interfaces and mixed signal devices can challenge timing closure. You may not have control over the pipelining or partitioning of IP blocks.

Nevertheless, your design must accommodate timing requirements for the IP in the system to achieve a fully functional design. If you are unable to completely meet performance requirements for any part of a design, the system may fail to function as you want.

This application note presents design independent techniques for timing closure. Whether you use Application Specific Standard Products (ASSPs), Application Specific Integrated Circuits (ASICs), or Field Programmable Gate Arrays (FPGAs), rapid timing closure poses a challenge for system design that you can overcome using these methods.

The Intel® Quartus® Prime Fitter's default settings are set to help you meet required timing constraints for most designs. However, for designs that cannot meet timing requirements with default settings, use the methodology in this application note to shorten design cycles, reduce complexity, and achieve timing closure requirements as quickly as possible.

Shorten Design Cycles

Typically, current FPGA systems are characterized by shorter product life cycles driven by market pressures. To be successful, designers must design, test, and bring the product to the market as quickly as possible. Often designers must prioritize design verification because delivering successful products at the first trial is essential for economic viability.

The Intel® Quartus® Prime software provides features that help you meet market pressure and stringent performance goals along with shorter design cycles. The Intel® Quartus® Prime software provides accurate timing models, advanced timing analysis, and fine-tuned Fitter algorithms to meet your goals.

With the default Intel® Quartus® Prime Compiler settings, you can often achieve push-button timing closure for typical FPGA designs. For those designs where push-button timing closure is difficult, the Intel® Quartus® Prime software helps you to plan for timing closure at the beginning of your design cycle to accelerate timing closure at the end of the cycle.

Reduce Timing Closure Complexities and Conflicts

Many factors can increase the difficulty of timing closure. For example, the placement of specific resources in a location on the FPGA could be a complexity. Specialty blocks, such as DSPs, RAMs, and transceivers are sometimes located in areas of the FPGA where routing availability can be problematic because of congestion around the blocks. Poor resource placement by the Fitter can result in timing not meeting all requirements.

Timing closure conflicts can occur between the resource, area, power, and timing requirements that you specify for your design. For example, often mobile devices must trade power for speed considerations. If your design requires more resources, you must distribute the resources across the target FPGA device. Widely distributed resources tend to have long interconnections. At smaller device geometries, delays are dominated by interconnect delays rather than cell delays. To have shorter net lengths, you ideally have a smaller area. Therefore, these two requirements generally conflict.

Another common timing closure conflict occurs between reliability and the time available for verification. Because of the reduced market window that dictates your product’s success, system designer's want to have a design working within the shortest amount of time, at the lowest possible cost, for a product that is simple, scalable, and reliable. To maximize the window of opportunity, you must shrink the design cycle. However, the requirement to have a successful design results in having to spend more time verifying the design. All of these complexities increase the challenge of closing timing on a design.

Follow these guidelines and methodology to improve productivity, close timing faster, and reduce the number of Compiler iterations: