AN 584: Timing Closure Methodology for Advanced FPGA Designs

ID 683145
Date 10/08/2021
Public
Document Table of Contents

1.5.2. Follow Synchronous Design Practices

Following synchronous design practices can simplify the specification of timing constraints.

Although asynchronous techniques might save time in the short run and seem easier to implement, asynchronous design techniques rely on propagation delays and clock skews that do not scale well between different device families or architectures.

Asynchronous circuits are prone to glitches and race conditions that can render the resulting implementation unreliable, increasing the complexity of constraints.

In the absence of appropriate constraints, synthesis or place-and-route tools may not perform the best optimizations, resulting in inaccurate timing analysis results.

Moreover, in a synchronous design, a clock signal triggers every event. With the Fitter working to achieve all timing requirements, a synchronous design behaves in a more reliable manner for all PVT conditions. Synchronous designs easily migrate to different device families or speed grades.

For more information about using synchronous design practices for FPGA designs, refer to Synchronous FPGA Design Practices in Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations.

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